1. Technical Field
This invention relates to testing a data processor, and more particularly to a method and apparatus for fault testing a clock distribution network in a data processor.
As is well known to those having skill in the art, a data processor includes numerous complex logic networks for carrying on data processing operations. Interconnecting all the logic networks is a clock distribution network. The clock distribution network is a fan-out network for a clock signal generated by a high frequency oscillator. The clock signal is distributed to all the logic networks in a predetermined timing relationship. In a large data processor, on the order of 15,000 distinct clock signal lines may be provided. Accordingly, the clock distribution network may comprise 5-7% of the integrated circuit chips in the data processor.
2. Background Art
The complexity of the logic and clock distribution networks in a large data processor presents extreme difficulties in the testing environment. Typically, tests are performed on the data processor prior to shipment. Internal tests are also generally performed by the data processor each time it is turned on to assure fault-free performance.
Many techniques ae known for fault testing the logic network portion of a data processor. For example, one widely known technique for testing a logic network is the Level Sensitive Scan Design (LSSD) technique wherein normally inaccessible logic points on an integrated circuit chip are accessed by means of a shift register latch network. The LSSD technique is described in detail in many publications and patents, for example, U.S. Pat. No. 3,783,254 entitled "Level Sensitive Logic System", E. B. Eichelberger and assigned to the assignee of the present invention. The LSSD technique allows the complex logic networks which form a data processor to be fully tested.
Techniques have heretofore not existed for fault testing the clock distribution network of a data processor. Generally each clock signal line in the clock distribution network is susceptible to two types of faults, referred to as "stuck-on" or "stuck-off" faults. A "stuck-on" fault, also referred to as a "hot clock", means that the clock signal line is still supplying a clock signal even though the clock distribution network is disabled. For example, a clock signal line which is short circuited to a power supply line would provide a "hot clock". A "stuck-off" fault, also referred to as a "cold clock", means that the clock signal line does not supply a clock signal even though the clock distribution network is enabled. For example, an open circuited clock signal line would provide a "cold clock".
Heretofore, when the clock distribution network failed (i.e., one or more clock signal lines become stuck-on or stuck-off), the defect would manifest itself as a defect in the logic network being supplied by the clock distribution network. While it would be known that the data processor as a whole had a defect, it could not be ascertained whether the defect arose in the logic network itself or in the clock distribution network. Moreover, even if it could be ascertained that the defect arose in the clock distribution network, it was heretofore impossible to isolate the defect to a particular clock signal line on a particular integrated circuit chip within the clock distribution network.